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Dr. Patrick Goh Kuan Lye

B.Sc (Illinois), M.Sc (Illinois), Ph.D (Illinois)
Tel : 04 - 599 6033
Email : Alamat emel ini dilindungi dari Spambot. Anda perlu hidupkan JavaScript untuk melihatnya.

dr patrick

 

Specializations


Signal Integrity, Interconnect Modeling and Simulation, High-speed Signaling

Research Interest


Signal and power integrity
Modeling and simulation methods for interconnects and packages
High-speed and high-frequency digital signaling
Thermal issues in integrated circuits
Artificial intelligence based methods (e.g. neural networks, genetic algorithm)
RF and microwave devices

Selected Publications

P. Goh and J. E. Schutt-Ainé, “Improving fast S-parameter convolution by optimising reference impedance,” IET Electronics Letters, vol. 50, no. 18, pp. 1290–1292, Aug. 2014. (IF: 1.068)

P. Goh and J. E. Schutt-Ainé, “The latency insertion method for simulations of phase-locked loops,” Journal of Computational Electronics, vol. 13, no. 2, pp. 529–536, Jun. 2014. (IF: 1.372)

P. Goh, J. E. Schutt-Ainé, D. Klokotov, J. Tan, P. Liu, W. Dai and F. Al-Hawari, “Partitioned latency insertion method (PLIM) with a generalized stability criteria,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 9, pp. 1447–1455, Sep. 2011. (IF: 1.236)

J. E. Schutt-Ainé, P. Goh, Y. Mekonnen, J. Tan, F. Al-Hawari, P. Liu, and W. Dai, “A comparative study of convolution and order reduction techniques for blackbox macromodeling using scattering parameters,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 10, pp. 1642–1650, Oct. 2011. (IF: 1.236)

D. Klokotov, P. Goh, J. E. Schutt-Ainé, “Latency insertion method (LIM) for DC analysis of power supply networks,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 11, pp. 1839–1845, Nov. 2011. (IF: 1.236)

J. E. Schutt-Ainé and P. Goh, “Comparing fast convolution and model order reduction methods for S-parameter simulation,” in Proc. IEEE Electr. Des. Adv. Packag. Syst. Symp., Nara, Japan, Dec. 2013, pp. 134–137. (Best Paper Award).

P. Goh, “Latency insertion method with MNA blocks via node tearing,” in 8th Int. Conf. Robotic, Vision, Signal Process. and Power Appl., Penang, Malaysia, Nov. 2013, pp. 401–408.

J. E. Schutt-Ainé and P. Goh, “ Phase-locked loop simulations using the latency insertion method,” in IEEE 4th Latin American Symposium on Circuits and Systems, Cusco, Peru, Feb. 2013, pp. 1–4.

P. Goh and J. E. Schutt-Ainé, “Latency insertion method (LIM) for CMOS circuit simulations with multi-rate considerations,” in Proc. 20th IEEE Electr. Perform. Electron. Packag., San Jose, California, USA, Oct. 2011, pp. 125–128.

P. Goh, J. E. Schutt-Ainé, D. Klokotov, J. Tan, P. Liu, W. Dai, and F. Al-Hawari, “Partitioned latency insertion method (PLIM) with stability considerations,” in Proc. 15th IEEE Workshop Signal Propagat. Interconn., Naples, Italy, May 2011, pp. 107–110.

P. Liu, J. Tan, Z. Zhou, J. E. Schutt-Ainé, and P. Goh, “A comparison of two latency insertion methods in dependent sources applications,” in Proc. 20th IEEE Electr. Perform. Electron. Packag., San Jose, California, USA, Oct. 2011, pp. 295–298.

P. Liu, J. Tan, Z. Zhou, J. E. Schutt-Ainé, and P. Goh, “Application of the amplification matrix latency insertion method to circuits with dependent sources,” in Proc. IEEE Electr. Des. Adv. Packag. Syst. Symp., Hangzhou, China, Dec. 2011, pp. 1–5.

J. E. Schutt-Ainé, D. Klokotov, P. Goh, J. Tan, F. Al-Hawari, P. Liu, and W. Dai, “Application of the latency insertion method to circuits with blackbox macromodel representation,” in Proc. 11th IEEE Electron. Packag. Technol. Conf., Singapore, Dec. 2009, pp. 92–95.

Grants

A pole-residue formulation for eye height/width analysis of high-speed interconnect signals using artificial neural networks. (USM RUI, Mar. 2017-Feb 2020, RM 83,600 – Project Leader)

Physically consistent fast transient simulations of large linear circuits using the latency insertion method. (USM Short Term Grant, Mar. 2014-Mar. 2016, RM 40,000 – Project Leader)

Novel robust control approach for critically stable systems with non-monotonic perturbations via IQC machinery and convex search algorithms. (FRGS, Aug 2016-July 2019, RM102,000 – Co-researcher)

Investigation of a new and fast algorithm for characterizations of high speed interconnects. (FRGS, May 2013-Apr. 2016, RM 124,000 – Co-researcher)

Research Topics

Application of Artificial Intelligence for Signal Integrity Analysis
Artificial intelligence (AI) techniques take advantage of advancements in machine learning to solve many challenging problems in engineering. Artificial neural networks (ANN) is an AI based algorithm which rely on a learning or training process where the algorithm is first fed with a well-established training set of data. The algorithm then, through a corrective process, adjusts its internal parameters such that it is able to solve subsequent inputs even though it has never encountered those before. An example structure of a multilayer perceptron (MLP) artificial neutral network is shown below. This research aims to apply ANN and other AI based methods to analyze signal quality in high-speed systems.
 

MLP based ANN with an input layer, one hidden layer and an output layer.

Modeling and Simulation of Power Distribution Networks on IC and PCB
The analysis of power distribution networks (PDN) on IC and PCB is vital to ensure proper operations of digital circuits. In addition, poor power distribution can also impair the quality of the high-speed signals through effects such as simultaneous switching noise (SSN), power ripples and ground bounce. Research on PDN modeling involves geometry discretization (normally using triangular or tetrahedral elements), followed by a circuit element extraction using algorithms such as those based on the Delaunay-Voronoi triangulation. Then, DC and transient PDN analysis can be carried out on the developed model. This research aims to combine existing modeling methods with a novel circuit simulation algorithm that synergizes with the PDN modeling process.
 

PDN modeling using triangular elements.

A New and Fast Algorithm for Characterizations of High-Speed Interconnects
Read the featured interview in IET Electronic Letters (vol. 52, issue 23) here:
http://ieeexplore.ieee.org/document/7728336/
Interconnect simulations for signal integrity analysis is a vital component to ensure proper operation of modern integrated circuit (IC) chips. However, interconnect simulations remain a challenge in the industry today due to the sheer large size of modern complex interconnect schemes. For example, it is common for a complete interconnect netlist to contain millions of nodes. When simulated in a conventional circuit simulation method such as SPICE, a single simulation could take hours or even days. This research attempts to find a new and novel idea for the characterization and simulation of high speed interconnects.
On-going projects include work on ensuring the stability of the algorithm, and improving the accuracy through the use of novel integration methods such as the Verlet integration and higher order Runge-Kutta methods.

Others:
In addition to the above projects, I also have topics in the following areas:
RF and microwave devices
Thermal issues in integrated circuits

 

Prospective students who would like to pursue an MSc or PhD either full-time or part-time in one of the above areas are invited to contact me at Alamat emel ini dilindungi dari Spambot. Anda perlu hidupkan JavaScript untuk melihatnya.. Financial assistance (monthly stipends) are available.

 

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