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Dr. Patrick Goh Kuan Lye

B.Sc (Illinois), M.Sc (Illinois), Ph.D (Illinois)
Tel : 04 - 599 6033
Email : Alamat emel ini dilindungi dari Spambot. Anda perlu hidupkan JavaScript untuk melihatnya.

dr patrick

Looking for potential MSc or PhD students to do research in the area of signal integrity, interconnect simulations, and related fields.
Students interested should contact Alamat emel ini dilindungi dari Spambot. Anda perlu hidupkan JavaScript untuk melihatnya.

Specializations


Signal Integrity, Interconnect Modeling and Simulation, High-speed Signaling

Research Interest


Signal and power integrity
Modeling and simulation methods for interconnects and packages
High-speed and high-frequency digital signaling
Thermal issues in integrated circuits
Artificial intelligence based methods (e.g. neural networks, genetic algorithm)
RF and microwave devices

Selected Publications


P. Goh and J. E. Schutt-Ainé, “Improving fast S-parameter convolution by optimising reference impedance,” IET Electronics Letters, vol. 50, no. 18, pp. 1290–1292, Aug. 2014. (IF: 1.068)

P. Goh and J. E. Schutt-Ainé, “The latency insertion method for simulations of phase-locked loops,” Journal of Computational Electronics, vol. 13, no. 2, pp. 529–536, Jun. 2014. (IF: 1.372)

P. Goh, J. E. Schutt-Ainé, D. Klokotov, J. Tan, P. Liu, W. Dai and F. Al-Hawari, “Partitioned latency insertion method (PLIM) with a generalized stability criteria,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 9, pp. 1447–1455, Sep. 2011. (IF: 1.236)

J. E. Schutt-Ainé, P. Goh, Y. Mekonnen, J. Tan, F. Al-Hawari, P. Liu, and W. Dai, “A comparative study of convolution and order reduction techniques for blackbox macromodeling using scattering parameters,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 10, pp. 1642–1650, Oct. 2011. (IF: 1.236)

D. Klokotov, P. Goh, J. E. Schutt-Ainé, “Latency insertion method (LIM) for DC analysis of power supply networks,” IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 11, pp. 1839–1845, Nov. 2011. (IF: 1.236)

J. E. Schutt-Ainé and P. Goh, “Comparing fast convolution and model order reduction methods for S-parameter simulation,” in Proc. IEEE Electr. Des. Adv. Packag. Syst. Symp., Nara, Japan, Dec. 2013, pp. 134–137. (Best Paper Award).

P. Goh, “Latency insertion method with MNA blocks via node tearing,” in 8th Int. Conf. Robotic, Vision, Signal Process. and Power Appl., Penang, Malaysia, Nov. 2013, pp. 401–408.

J. E. Schutt-Ainé and P. Goh, “ Phase-locked loop simulations using the latency insertion method,” in IEEE 4th Latin American Symposium on Circuits and Systems, Cusco, Peru, Feb. 2013, pp. 1–4.

P. Goh and J. E. Schutt-Ainé, “Latency insertion method (LIM) for CMOS circuit simulations with multi-rate considerations,” in Proc. 20th IEEE Electr. Perform. Electron. Packag., San Jose, California, USA, Oct. 2011, pp. 125–128.

P. Goh, J. E. Schutt-Ainé, D. Klokotov, J. Tan, P. Liu, W. Dai, and F. Al-Hawari, “Partitioned latency insertion method (PLIM) with stability considerations,” in Proc. 15th IEEE Workshop Signal Propagat. Interconn., Naples, Italy, May 2011, pp. 107–110.

P. Liu, J. Tan, Z. Zhou, J. E. Schutt-Ainé, and P. Goh, “A comparison of two latency insertion methods in dependent sources applications,” in Proc. 20th IEEE Electr. Perform. Electron. Packag., San Jose, California, USA, Oct. 2011, pp. 295–298.

P. Liu, J. Tan, Z. Zhou, J. E. Schutt-Ainé, and P. Goh, “Application of the amplification matrix latency insertion method to circuits with dependent sources,” in Proc. IEEE Electr. Des. Adv. Packag. Syst. Symp., Hangzhou, China, Dec. 2011, pp. 1–5.

J. E. Schutt-Ainé, D. Klokotov, P. Goh, J. Tan, F. Al-Hawari, P. Liu, and W. Dai, “Application of the latency insertion method to circuits with blackbox macromodel representation,” in Proc. 11th IEEE Electron. Packag. Technol. Conf., Singapore, Dec. 2009, pp. 92–95.

 

Grants


Physically Consistent Fast Transient Simulations of Large Linear Circuits Using the Latency Insertion Method. (USM Short Term Grant, Mar. 2014-Mar. 2016, RM 40,000 – Project Leader)

Investigation of a new and fast algorithm for characterizations of high speed interconnects. (FRGS, May 2013-Apr. 2016, RM 124,000 – Co-researcher)

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