Guest Lecture (Industry in Class) with Mr. Daniel Kho
Nibong Tebal, 17th October 2019 - A Guest Lecture (Industry in Class) was recently delivered by Mr Daniel Kho, SMIEEE of LogikHaus. The lecture entitled "FPGA and ASIC Digital Design Development" was conducted in BK3 as part of EEE378 Digital Electronics II course for 3rd year Electronic Engineering students.
The lecture covered an overview of the digital IC development process starting from the top-level mathematical modelling, front-end and back-end hardware design, and down to the bottom-level pre-silicon design verification stages. The hardware design topics include RTL design entry using Hardware Description Languages such as VHDL and SystemVerilog, logic synthesis, physical design layout covering automatic place and route (APR) and clock tree synthesis (CTS), and design optimisations in order to meet the design constraints. On the other hand, the pre-silicon design verification topics include functional simulations using standard methodologies like OS-VVM or UVM, formal netlist verification, and physical verification using static timing analysis (STA), thermal optimisation, etc.
Several concepts learnt during the course were also mentioned in the lecture such as logic design and minimisation, K-maps, arithmetic circuits, etc. highlighting their significance in a hierarchical design approach. We hope that the students gained deeper understandings from this guest lecture on the real application of the theories covered in the normal lectures.
We extend our thanks to Mr Daniel Kho for sharing his valuable knowledge and experiences. It was a great lecture given by a professional practitioner with over 16 years of industrial experience.
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